Senior Staff Engineer, Packaging


NASHUA, NH, US, 3062

pSemi Corporation is a Murata company driving semiconductor integration. pSemi builds on Peregrine Semiconductor’s 30-year legacy of technology advancements and strong IP portfolio but with a new mission—to enhance Murata’s world-class capabilities with high-performance semiconductors. With a strong foundation in RF integration, pSemi’s product portfolio now spans power management, connected sensors, optical transceivers, antenna tuning and RF frontends. These intelligent and efficient semiconductors enable advanced modules for smartphones, base stations, personal computers, electric vehicles, data centers, IoT devices and healthcare. From headquarters in San Diego and offices around the world, pSemi’s team explores new ways to make electronics for the connected world smaller, thinner, faster and better.

Job Summary

Reporting to the Director of Platform engineering of the power semiconductor business unit, this individual will be responsible for all aspects of power semiconductor packaging, working closely with our engineering team to support product during the entire product life cycle from product definition through product release to volume production and post-production package related works through OSAT. Fully conversant with advanced power semiconductor packaging technology, the successful candidate will be a part of a cross-functional product development team critical for bringing state-of-art power management products to market.


Roles & Responsibilities

This position has responsibility for:

  • Implementing and maintenance of power semiconductor packaging technology process flows suitable for use in high volume, high reliability, industrial, datacoms, telecoms and commercial applications like laptop or handset devices.
  • Detailed product packaging design including use of simulation tools to assess design integrity and performance such as modeling of parasitic losses, thermal dissipation, mechanical stress etc.
  • Guide design team what they should do or not based on the experiences with power, well familiar with OSATs and their roadmaps.
  • Developing a forward-looking packaging roadmap that is aligned with our product roadmap, work with design engineering understanding their needs. Validating and qualifying new packaging technologies ahead of new product development.
  • Working seamlessly with our power semiconductor chip architects from concept stage through to final product realization to assure highly optimized designs that maximize product performance with highest possible field reliability.
  • Close collaboration with cross functional team members to assure on-time delivery of new products through all aspects of design and qualification including production, test engineering, characterization, quality, reliability, and sustaining engineering.
  • Close collaboration with key supply chain partners, including wafer fabs, OSATs, outsourced test and characterization organizations, and logistics.
  • Sign-off on PCB designs for all critical boards (REL/EVB/etc), documentation inputs for customer datasheets and application notes relating to soldering profile, thermal considerations, reliability etc.


Competency Requirements

In order to perform the job successfully, an individual should demonstrate the following competencies:

  • Driving for Results: Aggressively pursues challenging goals and objectives; will put in considerable time and effort to accomplish objectives; takes a highly focused, goal driven approach toward work
  • Acting Decisively: Moves quickly to make decisions and commit to a clear course of action; comfortable making decisions based on partial information; willing to take risks in order to maintain momentum; shows a strong bias toward action
  • Acting as a Champion for Change: Challenges the status quo; encourages people to question existing methods, practices, and assumptions; supports people in their efforts to try new things
  • Critical thinking:  Skilled at finding logical flaws in arguments and plans; identifies problems and solutions that others might miss; provides detailed insight and constructive criticism into problems and complex situations
  • Working with Ambiguity: Achieves forward progress in the face of poorly defined situations and/or unclear goals; able to work effectively with limited or partial information


Minimum Qualifications (Experience and Skills)

  • Typically requires 8 to 12 years of experience in power-semiconductor packaging.
  • 2+ years project or technical leadership.
  • Thorough understanding and demonstrated experience in the use of advanced packaging technologies, including WLCSP, FCOL, CuP, MCM, embedded die in substrate, passive component in package, single-side/double-side component in package, back-side die attach etc.
  • Thorough understanding and demonstrated design experience in advanced Wafer level Solder Bump and Copper Pillar Technologies, WLCSP, Wirebond, Flip Chip leadframe and MIS, SiP, LGA, BGA semiconductor packaging technologies.
  • Thorough understanding of semiconductor package materials and assembly stack-ups and their impact on product performance.
  • Thorough understanding of all aspects of semiconductor manufacturing from wafer through to final product.
  • Power-semiconductor background with strong analog/mixed-signal design experience and thorough understanding of the impact of packaging with regards to product performance.
  • Hands-on experience with simulation tools to assess product design integrity.
  • Experience in working together with quality organization to implement and maintain best practice in reliability measures such as ESD, HTOL, etc., including assessing potential reliability and quality risks due to package construction, conducting FMEA.
  • Si-Power management IC packaging experience for ~10x10mm die with many functional pins. Using Cu-Pillar Lead Frame QFN. This expectation is different from the discrete power FET.
  • 2D & 3D CAD Drawing & Modeling, Autodesk Inventor, SolidWorks or similar. Complete and improve the current CAD models of the proposed pSemi semiconductor packages.
  • Classical Analysis: Thorough Classical understanding of Material Science, Fluid Mechanics, Heat Transfer and Mechanics of Materials (Elastic and Plastic), ability to create simple models of complex systems for use in first checks, predictors and feasibility studies.
  • CAD Modeling & FEA Simulation: Experience with Mechanical FEA Modeling & Simulation Tools, ANSYS Workbench, Static and Transient analysis. Analyze the model results based on the assigned loads and conditions, understand the key material and geometry attributes contributing to the results. Review the corresponding models’ predictions based on actual lab performance and adjust the model and its parameters to align with the measured results


Preferred Qualifications

  • Recent experience in DC-DC power packaging development


Education Requirements

  • Bachelor’s degree in Electrical, Mechanical, Materials and/or Chemical Engineering or related discipline; Master’s or PhD preferred


Work Environment

This job operates in a professional office environment. This role routinely uses standard office equipment.


Physical Demands

The physical demands described here are representative of those that must be met by an employee to successfully perform the essential functions of this job. While performing the duties of this job, the employee is regularly required to talk or hear. The employee frequently is required to stand; walk; use hands to finger, handle or feel; and reach with hands and arms. Specific vision abilities required by this job include close vision, distance vision, color vision, peripheral vision, depth perception and ability to adjust focus. This position requires the ability to occasionally lift office products and supplies, up to 20 pounds.



USD 144,932.33 - 188,422.46 per year



pSemi Corporation supports a diverse workforce and is committed to a policy of equal employment opportunity for applicants and employees. pSemi does not discriminate on the basis of age, race, color, religion (including religious dress and grooming practices), sex/gender (including pregnancy, childbirth, or related medical conditions or breastfeeding), gender identity, gender expression, genetic information, national origin (including language use restrictions and possession of a driver’s license issued under Vehicle Code section 12801.9), ancestry, physical or mental disability, legally-protected medical condition, military or veteran status (including “protected veterans” under applicable affirmative action laws), marital status, sexual orientation, or any other basis protected by local, state or federal laws applicable to the Company. pSemi also prohibits discrimination based on the perception that an employee or applicant has any of those characteristics, or is associated with a person who has or is perceived as having any of those characteristics.

Note: The Peregrine Semiconductor name, Peregrine Semiconductor logo and UltraCMOS are registered trademarks and the pSemi name, pSemi logo, HaRP and DuNE are trademarks of pSemi Corporation in the U.S. and other countries. All other trademarks are the property of their respective companies. pSemi products are protected under one or more of the following U.S. Patents:

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