Senior NPI Packaging Engineer

pSemi Corporation is a Murata company driving semiconductor integration. pSemi builds on Peregrine Semiconductor’s 30-year legacy of technology advancements and strong IP portfolio but with a new mission—to enhance Murata’s world-class capabilities with high-performance semiconductors. With a strong foundation in RF integration, pSemi’s product portfolio now spans power management, connected sensors, optical transceivers, antenna tuning and RF frontends. These intelligent and efficient semiconductors enable advanced modules for smartphones, base stations, personal computers, electric vehicles, data centers, IoT devices and healthcare. From headquarters in San Diego and offices around the world, pSemi’s team explores new ways to make electronics for the connected world smaller, thinner, faster and better.

Job Summary

This position assists with all aspects of semiconductor packaging through all phases of product development which includes early concept feasibility, prototyping, product qualification, and product transition to production.  The individual is fully conversant with microelectronics packaging technologies and has in-depth understanding of the interactions between manufacturing processes, verification testing, and quality assurance methodology.  This individual facilitates the interests of packaging on cross functional engineering teams.  This position must enjoy working in a fast-paced environment while maintaining a sense of commitment and be flexible to project needs. The position must be a team player and possess a sense of urgency to meet product requirements on schedule.

Roles & Responsibilities

This position has responsibility for:

• Responsible for design of bump, package, and assembly process flow for new products for use in high volume, high reliability, industrial, commercial, and automotive applications and will use data analysis to drive most decisions.
• Contributes to a forward-looking packaging roadmap and aligns with product line roadmaps and other technology roadmaps.
• Researches new packaging technologies and or suppliers to facilitate and propel product line roadmaps in a highly competitive market landscape.
• Develops manufacturing processes and documents process capabilities in the form of design rules for product development teams.
• Creates early concept sketches in support of technology recommendations, collects cost estimates in support of customer facing product opportunity pursuits.
• Assists cross functional design teams with making appropriate design decisions related to packaging and assembly processes for both prototype and high-volume manufacturing.
• Performs cost and risk assessments for new product designs against known design rules.
• Detailed package design including the use of tolerance analysis and simulation tools to assess design integrity and performance for mechanical and thermal reliability as well as manufacturing producibility.
• Prepares design documentation and bill of materials for both chip fabrication, backend wafer processes, and component assembly.
• Execution of DoE experiments collecting characterization data to substantiate design decisions and mitigate technical risk to new products in development.
• Collaborates with internal support personnel and other key supply chain partners including wafer fabs, offshore assembly and test contractors, and 3rd party service providers with service needs for specific technology or product developments.
• Supports failure analysis and problem resolution in the development process or production environment
• Mentor junior engineers in the packaging and assembly disciplines.

Minimum Qualifications (Experience and Skills)

• Bachelor of Engineering (Packaging, Electrical, Mechanical, Materials or Chemical), Physics or Chemistry.
• 5 years of experience in electronics packaging with Bachelors (3yrs with Masters, with PhD). Work experience must include hands-on experience in specific packaging technology discipline.
• Experience with package assembly process development.
• Understands material properties and interactions with manufacturing processes.
• Hands on experience with design tools such as AutoCAD and Cadence Allegro (or equivalent).
• Demonstrated experience driving packaging technology developments.
• Hands on experience with manufacturing equipment and processing.
• Experience working with 3rd party suppliers.
• Familiarity with DOE methodology.
• Ability to present highly technical information to non-technical personnel.
• Familiarity with Microelectronic packaging technologies such as flip chip bumping, wafer backend processing, SMT, flip chip attach, flux cleaning, overmold, package marking, dicing, test, and packaging for shipment.

Education Requirements

• Bachelor’s in Engineering (Packaging, Electrical, Mechanical, Materials or Chemical), Physics or Chemistry; MS preferred

Work Environment

This job operates in a professional office environment. This role routinely uses standard office equipment.

Physical Demands

The physical demands described here are representative of those that must be met by an employee to successfully perform the essential functions of this job. While performing the duties of this job, the employee is regularly required to talk or hear. The employee frequently is required to stand; walk; use hands to finger, handle or feel; and reach with hands and arms. Specific vision abilities required by this job include close vision, distance vision, color vision, peripheral vision, depth perception and ability to adjust focus. This position requires the ability to occasionally lift office products and supplies, up to 20 pounds.

USD 122,199.70 - 158,868.41 per year

pSemi Corporation supports a diverse workforce and is committed to a policy of equal employment opportunity for applicants and employees. pSemi does not discriminate on the basis of age, race, color, religion (including religious dress and grooming practices), sex/gender (including pregnancy, childbirth, or related medical conditions or breastfeeding), gender identity, gender expression, genetic information, national origin (including language use restrictions and possession of a driver’s license issued under Vehicle Code section 12801.9), ancestry, physical or mental disability, legally-protected medical condition, military or veteran status (including “protected veterans” under applicable affirmative action laws), marital status, sexual orientation, or any other basis protected by local, state or federal laws applicable to the Company. pSemi also prohibits discrimination based on the perception that an employee or applicant has any of those characteristics, or is associated with a person who has or is perceived as having any of those characteristics.

Note: The Peregrine Semiconductor name, Peregrine Semiconductor logo and UltraCMOS are registered trademarks and the pSemi name, pSemi logo, HaRP and DuNE are trademarks of pSemi Corporation in the U.S. and other countries. All other trademarks are the property of their respective companies. pSemi products are protected under one or more of the following U.S. Patents: http://patents.psemi.com