Technical Director, Digital Design and Verification

pSemi Corporation is a Murata company driving semiconductor integration. pSemi builds on Peregrine Semiconductor’s 30-year legacy of technology advancements and strong IP portfolio but with a new mission—to enhance Murata’s world-class capabilities with high-performance semiconductors. With a strong foundation in RF integration, pSemi’s product portfolio now spans power management, connected sensors, optical transceivers, antenna tuning and RF frontends. These intelligent and efficient semiconductors enable advanced modules for smartphones, base stations, personal computers, electric vehicles, data centers, IoT devices and healthcare. From headquarters in San Diego and offices around the world, pSemi’s team explores new ways to make electronics for the connected world smaller, thinner, faster and better.

Job Summary

The Technical Director oversees the Digital Design and Verification teams in San Diego, Austin, and the pSemi India Design Center (IDC) in Chennai. This role is responsible for building and developing high‑performing engineering teams, driving digital design strategy, defining verification methodologies, and ensuring high‑quality and timely project execution. The director collaborates closely with cross‑functional groups—including Marketing, Product Engineering, and Test Engineering—to support products from definition through mass production.

Roles & Resposibilities

• Lead and manage digital design and verification teams across multiple global sites.
• Architect, design, and verify digital logic to meet power, performance, and area objectives.
• Improve team efficiency, productivity, and design quality through methodology and flow enhancements.
• Conduct architecture, design, and verification reviews throughout the project lifecycle.
• Support front-end and mid‑end tasks such as synthesis, timing closure, DFT, and ATPG.
• Support back-end tasks such as place-and-route, DRC, LVS, parasitic extraction, and back annotation of delays for timing closure.
• Support test vector generation, silicon validation, and digital characterization activities.
• Contribute to AMS verification and mixed‑signal product development.
• Identify automation and tool requirements with cross‑functional partners.
• Guide products through qualification and into high‑volume production.

Minimum Qualifications (Experience & Skills)

• 15+ years of experience in digital design and verification.
• 5+ years of experience managing engineering teams.
• Strong strategic thinking and performance‑management abilities.
• Excellent communication and leadership skills with the ability to simplify complex concepts and mentor engineers.
• Proven project‑management experience across multiple concurrent programs.
• Broad experience in ASIC systems, digital architecture, design, verification/validation, mid/back‑end coordination, product development, and mass‑production release.
• Key Technical Competencies:

• Strong foundation in digital circuits, transistor‑level design, system architecture.
• Deep expertise in RTL/Verilog and familiarity with mid/back‑end design.
• Proficiency in front‑end digital design, including timing and synthesis.
• Experience designing state machines, serial interfaces, and integrating IP (SRAM, OTP).
• Knowledge of common interface protocols (e.g., MIPI RFEE, SPI, I2C, I3C).
• Experience with advanced process nodes and low‑power design techniques.
• Strong understanding of clock‑domain crossing, power domains, and design‑for‑low‑power.
• Knowledge of DSP architectures and signal‑processing ASICs.
• Proficiency in C/C++, C#, Perl, Python, Tcl, and Makefiles.
• Extensive experience with Cadence and Synopsys toolchains.
• Familiarity with SystemVerilog, UVM, and post‑silicon validation workflows.
• Knowledge of DFT, including scan and memory BIST.

Preferred Qualifications

• Knowledge of Comm.Systems and DSP architectures in signal processing ASICs, as well as mixed signal design, including delta‑sigma modulators, discrete-time systems, z-domain analysis, digital filters and fixed‑point arithmetic implementations.
• Experience in modeling control loops and DSP algorithms using MATLAB/Simulink.
• Experience integrating and validating mixed‑signal IP and developing digital logic for calibration and control.
• FPGA‑based validation experience.
• Experience with standard‑cell library development and characterization.
• Experience in behavioral modeling of RF and AMS circuits for ASIC-level verification.
• Knowledge of UVM‑based verification techniques.
• Experience in IP development, integration, and semiconductor product lifecycle management.
• Experience working with global, cross‑functional design teams.

Education Requirements

• Master’s or PhD in Electrical Engineering, Computer Engineering, or an equivalent degree with relevant experience.

Work Environment

This job operates in a professional office environment. This role routinely uses standard office equipment.

Physical Demands

The physical demands described here are representative of those that must be met by an employee to successfully perform the essential functions of this job. While performing the duties of this job, the employee is regularly required to talk or hear. The employee frequently is required to stand; walk; use hands to finger, handle or feel; and reach with hands and arms. Specific vision abilities required by this job include close vision, distance vision, color vision, peripheral vision, depth perception, and ability to adjust focus. This position requires the ability to occasionally lift office products and supplies, up to 20 pounds.

USD 212,186.16 - 291,755.96 per year

pSemi Corporation supports a diverse workforce and is committed to a policy of equal employment opportunity for applicants and employees. pSemi does not discriminate on the basis of age, race, color, religion (including religious dress and grooming practices), sex/gender (including pregnancy, childbirth, or related medical conditions or breastfeeding), gender identity, gender expression, genetic information, national origin (including language use restrictions and possession of a driver’s license issued under Vehicle Code section 12801.9), ancestry, physical or mental disability, legally-protected medical condition, military or veteran status (including “protected veterans” under applicable affirmative action laws), marital status, sexual orientation, or any other basis protected by local, state or federal laws applicable to the Company. pSemi also prohibits discrimination based on the perception that an employee or applicant has any of those characteristics, or is associated with a person who has or is perceived as having any of those characteristics.

Note: The Peregrine Semiconductor name, Peregrine Semiconductor logo and UltraCMOS are registered trademarks and the pSemi name, pSemi logo, HaRP and DuNE are trademarks of pSemi Corporation in the U.S. and other countries. All other trademarks are the property of their respective companies. pSemi products are protected under one or more of the following U.S. Patents: http://patents.psemi.com