Custom Analog IC Layout Engineer

Location:

Waltham, MA, US, 02451

Eta Wireless is solving the fundamental problem of RF power amplifier power consumption in communications devices. We pioneered Digital Envelope Tracking (DET) technology and have since been acquired by Murata Manufacturing in September 2021. Eta is a multi-disciplinary, multi-national team of engineers with expertise spanning RF systems, power electronics, integrated circuits, embedded systems, software, algorithms, and module design. The breadth of expertise allows us to solve challenging problems with creative and disruptive solutions at tier-one customers.

Why Consider This Job Opportunity

The Custom Analog IC Layout Engineer designs layouts for high-current and high-voltage transistors, regulators as well as related analog blocks. This position ensures optimal current handling, EM reliability, and thermal performance. The Custom Analog IC Layout Engineer specializes in power device layout for high-performance, high-reliability analog, and mixed-signal integrated circuits. The role is accountable for the physical layout of power transistors, pass devices, high-current drivers, regulators, and related analog circuitry, working closely with circuit designers from concept through tape-out. The ideal candidate has a deep understanding of high-voltage and high-current layout practices, electromigration limits, parasitic reduction, and thermal management in custom ICs.

What To Expect (Essential Job Responsibilities)

Perform custom layout of power transistors, high-current regulators, ESD clamps, and other power handling circuits in CMOS, BCD, or similar processes.
Collaborate with designers on floor planning to optimize current paths, thermal dissipation, and area utilization.
Apply advanced layout techniques for matching, common centroid, and guard rings, as well as wide-metal routing, and current balancing.
Ensure compliance with foundry DRC, LVS, and ERC requirements and address design rule issues proactively.
Minimize parasitic resistance and capacitance in high-current paths for optimal efficiency.
Support parasitic extraction, electromigration verification, and thermal analysis.
Assist in chip-level integration and contribute to layout reviews with multidisciplinary teams.

What Is Required (Qualifications)

3+ years of industry experience in custom analog IC layout with a focus on power devices.
Experience with LDMOS, wide-metal routing, guard rings, and advanced matching techniques is preferred.
Proficiency in Cadence Virtuoso and PVS/Assura.
Strong understanding of power device layout best practices which include EM, thermal impact, HV spacing, and layered interconnect routing.
Experience with multiple technology nodes, BCD preferred; high-voltage CMOS, or analog process flows.

How To Stand Out (Preferred Qualifications)

Familiarity with high-voltage MOSFET layout and LDMOS structures.
Experience with DFM techniques, yield improvement, and layout automation/scripting (SKILL, Python).
Knowledge of packaging technologies (solder balls, RDL, CuP) and package-level thermal/electrical constraints for power ICs.
Experience with foundry release processes.
Bachelor’s degree in Electrical Engineering, EET, or equivalent.

Perks

Comprehensive benefits package including medical, dental, and vision insurance.
Generous Paid Time Off including paid holidays and floating holidays.
401(k) employer match on retirement planning.
Hybrid working schedule for eligible positions.
Tuition reimbursement on approved programs.
Flexible and health spending accounts.
Talent Development program.

Equal Opportunity/Affirmative Action Employer - M/F/Disabilities/Veterans